Field
The disclosed technology relates to the field of analog to digital conversion. In particular, the disclosed technology includes a circuit and a method for converting an analog signal to a digital value representation, the circuit comprising an incremental sigma-delta analog-to-digital converter.
Description of the Related Technology
Analog sensor measurements may need to be converted to digital value representations by an analog-to-digital converter (ADC) for processing. An incremental sigma-delta ADC enables high resolution analog-to-digital conversion. The measurement result represented by the analog signal is input as a constant voltage to the incremental sigma-delta ADC. The incremental sigma-delta ADC samples the constant voltage a number of times, M. By increasing the oversampling M, the incremental sigma-delta ADC improves the resolution as the quantization noise is suppressed.
However, in order to achieve a high resolution, the number of samples M needs to be large. Thus, the incremental sigma-delta ADC is associated with a timing constraint, such that the speed of the incremental sigma-delta ADC may be unsatisfactory.
In particular, where measurement results are sequentially acquired, the incremental sigma-delta ADC needs to be able to convert the analog signal to the digital value representation to match a rate at which the measurement results are acquired.
For instance, in imaging devices, pixels may detect light and the detected light forms an analog measurement result that is to be converted to a digital value representation. The analog measurement result is kept stable for a limited time by the pixel. The incremental sigma-delta ADC needs to be sufficiently fast in order to obtain a number of samples during the time that the analog measurement result is stable and convert the analog measurement result to the digital value representation with a satisfactory resolution.
Kim, J.-H. et al, “A 14b Extended Counting ADC Implemented In a 24 Mpixel APS-C CMOS Image Sensor”, International Solid-State Circuits Conference, ISSCC, 390-392, February 2012, disclose a two-step conversion of an analog signal in order to reduce conversion time. The two-step conversion uses an incremental sigma-delta ADC which provides a coarse conversion and a cyclic ADC, which is very fast and converts a residue from the incremental sigma-delta ADC to a fine-ADC level. However, this requires a complex circuit using a cyclic ADC in combination with the incremental sigma-delta ADC and will suffer from mismatch between the 2 converting steps.